This invention relates to methods of, and devices used for, repackaging semiconductor integrated circuit (xe2x80x9cICxe2x80x9d) packages, including ball-grid arrays (xe2x80x9cBGAsxe2x80x9d), quad flat packs (xe2x80x9cQFPsxe2x80x9d), and dual in-line packages (xe2x80x9cDIPsxe2x80x9d) in order to perform failure analysis (xe2x80x9cFAxe2x80x9d) thereon. More particularly, and not by way of any limitation, the present invention is directed to a method that provides a semiconductor IC sample for FA from the front side or backside using a variety of FA techniques, including electron microscopy (xe2x80x9cEMxe2x80x9d) and externally induced voltage alteration (xe2x80x9cXIVAxe2x80x9d).
FA is concerned with analyzing semiconductor IC devices for defects and failure mechanisms. A number of different techniques are available for performing FA on the front side or backside of a semiconductor IC device.
One technique for performing FA on a semiconductor IC device is emission microscopy (xe2x80x9cEMxe2x80x9d). FA using an emission microscope is performed by collecting visible and near infrared (xe2x80x9cNIRxe2x80x9d) wavelength photons emitted from transistors, junctions, and other photon generating structures on or near the top or front, electrically active, silicon surface. These photons are transmitted through the overlying, relatively transparent dielectric layers, passing between or scattered around the patterned, opaque metal interconnections. Detection of photons that emerge from around these overlying layers is referred to as front side EM analysis. Imaging light passing through the silicon substrate and emerging from the bottom is referred to as backside EM analysis.
The backside of the semiconductor IC device is the exposed surface opposite to that on which active semiconductor devices are fabricated. Backside analysis takes advantage of silicon""s transmission of photons with energies less than its indirect silicon band-gap energy. There is an increasing interest in backside EM analysis, which is driven, in part, by the advancement of semiconductor IC fabrication technologies with additional opaque conductor layers and packaging technologies that typically obscure the front side of the die. Restrictions in performing front side analysis is particularly acute with respect to BGA devices. While BGA packages that are fully populated allow more signal pins for a given package footprint, this configuration provides difficulties in using EM equipment for backside analysis.
Traditional backside EM typically requires polishing of the die from the backside and socketing the resultant die sample in a special fixture for inspection with NIR energies through the polished silicon substrate. Semiconductor IC sample preparation for backside analysis requires a semiconductor IC sample to remain in the original package or wafer and be imaged through the bottom of the socket that makes electrical contact to the semiconductor IC. But this method of backside EM analysis is not possible with BGAs with high pin populations.
XIVA comprises another set of techniques for performing FA on a semiconductor IC device and includes, among other techniques, light induced voltage alteration (xe2x80x9cLIVAxe2x80x9d), thermally induced voltage alteration (xe2x80x9cTIVAxe2x80x9d), charge induced voltage alteration (xe2x80x9cCIVAxe2x80x9d) and low energy charge induced voltage alteration (xe2x80x9cLeCIVAxe2x80x9d). These techniques take advantage of a change in voltage across a device under test as a reaction to some energy stimulus. In performing FA using XIVA techniques, a power supply to the semiconductor IC device is placed in constant current mode. The current is adjusted to provide the voltage required for the test or the response required for the voltage monitoring amplifier. The voltage monitoring amplifier is place in parallel with the power supply to monitor the voltage across the semiconductor IC device. The voltage monitoring amplifier is adjusted to null out the constant voltage being supplied by the power supply. When the energy source of the XIVA system is scanned across the semiconductor IC device, any change in voltage across the semiconductor IC device is detected by the voltage monitoring amplifier. The output signal of the voltage monitoring amplifier is fed to an optical microscope or other suitable monitoring device for determination of the location of a defect or other anomaly. Other techniques of FA, described below, include Schleeren Thermal Mapping, picoseconds imaging circuit analysis (xe2x80x9cPICAxe2x80x9d) and laser voltage probe (xe2x80x9cLVPxe2x80x9d).
LIVA and TIVA require backside access to the semiconductor IC device. LIVA utilizes a highly focused light source, generally a laser with a wavelength capable of penetrating the backside of the semiconductor IC device. The wavelength of the light is such that it interacts with the junctions within the semiconductor IC device creating hole-electron pairs in the junctions. In those locations where the circuit is anomalous, the hole-electron pairs combine to set up a current which disrupts the expected results of the circuit. The disruption is detected by the XIVA system.
TIVA also uses a highly focused light source, generally a laser with a wavelength which is capable of penetrating the backside of the semiconductor IC device. The wavelength of the light is such that it does not interact with the junctions. However, the wavelength of the light is such that it is adsorbed by the conductive lines which are constructed within the semiconductor IC device. The light heats up the conductors within the semiconductor IC device causing changes in the resistivity of the interconnections. The changes in resistivity are registered as changes in voltage across the semiconductor IC device. The light intensity is controlled to give the required heating to produce the desired signal which is detected by the XIVA system.
CIVA uses an electron beam to penetrate the top surface of a semiconductor IC device. The metal level within the semiconductor IC device which is activated is dependent upon the energy of the primary electron beam generated by a scanning electron microscope. For example, top level metal may only require 10 KeV to contact. Lower level metal may require 20 KeV. The primary electron beam penetrates to a metal level depositing a charge on that level. A metal line which is not electrically connected to a path to power or ground would float. The change in voltage level on the metal line changes the operation of the complementary CMOS pair in the semiconductor IC device and causes a resultant voltage change at the device power supply which would be detected by the XIVA system.
The LeCIVA technique uses an extremely high current, 200+nA primary electron beam, at low energy, typically 800 eV, to charge the surface of the semiconductor IC device. The gaussian energy distribution of the primary beam creates zones within the beam spot which charge differently. The very high current center charges the surface non-linearly with respect to the lower beam current on the outer edges of the beam spot. On the outer edges, the charging follows the non-linear charging rules for voltage and current by an electron beam. As the beam is scanned across the surface of the semiconductor IC device, the differential charging of the outer edge of the beam and the interior of the beam cause a voltage spike to occur which propagates through the dielectric. Metal lines block the signal. The voltage spike will change the voltage on any metal line which does not have a connection to power or ground. The change in voltage affects the complementary CMOS transistors to which the metal line is connected. Due to the change in current draw of the circuit, a change in voltage is seen across the semiconductor IC device which is detected by the XIVA system.
In Schleeren Thermal Mapping, laser light is used to light the backside of the semiconductor IC device. The reflected light passes across a single sided slit and is imaged on a viewing plane. Because some of the reflected signal is cut offby the slit, the resultant image is subject to interference patterns if there are any anomalies on the surface. Thus, with Schleeren Thermal Mapping, the backside of the semiconductor IC device is assumed to be polished flat and coated with some form of anti-reflective material. A change in the index of refraction of the silicon due to local heating when the semiconductor IC device is powered reveals the anomalies.
PICA images the photon emission of hot electrons injected into the channel of a transistor at the time the transistor is turned on. An optical microscope system with an imaging photo-multiplier is used to focus on a region of the semiconductor IC device, viewing multiple transistors. As the transistors are turned on, photons are focused into the detection system. A database is created correlating the X/Y positions of photon emission to the time of photon generation with respect to a reference signal. The database is used to create images of the transistors turning on with time resolution. Alternatively, a waveform can be created from the photon timing information at each transistor location.
LVP takes advantage of the Frank-Keldysh effect. A laser beam composed of a wavelength of light that is transparent to the silicon is focused on the junctions within the semiconductor IC device from the backside of the device. The wavelength of the laser beam is short enough to interact with the junctions causing some generation of hole-electron pairs. The light is reflected from the semiconductor by the silicide over the diffused areas or the metal in the contacts. The reflected light carries two pieces of information. There is an amplitude change in the reflected light due to changes in the junction and there are changes in phase due to changes in the electric field of the junction. The changes in the junction are due to changes in applied voltage on the junction. A detector system is used to pick up the changes in amplitude and or phase in the reflected light. The detector system converts the signal to a display which represents the voltage change on the junction.
The technology of semiconductor IC device preparation for the above referenced and other modes of FA is beset with various drawbacks and deficiencies. As such, it should be realized that there has arisen a need for a solution that addresses the shortcomings of the current semiconductor IC device preparation techniques. The present invention provides such a solution.
Accordingly, the present invention advantageously provides a system and method for preparing semiconductor IC devices, particularly BGAs, QFPs and DIPs for FA. Although many types of samples prepared using the disclosed method and invention can be prepared for backside FA, the disclosed method and invention can also be used for front side FA. The disclosed system and method is illustrated using a BGA type package, although other packages are easily adapted for repackaging using the disclosed method and invention. This system and method requires precision thinning and polishing of the semiconductor IC device to expose the backside of the die.